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Senior FPGA Design Electrical Engineer II

The Electronic Warfare Department (EWS) department is looking for experienced FPGA firmware designers to work with leading edge FPGA and ASIC designs. EWS is located in the Dallas/McKinney area. The EWS center provides a fast paced and dynamic work environment with opportunity both skill and job advancement. EWS is responsible for implementing digital designs for advanced Giga Hertz RF digital algorithms. Opportunities exist for advanced digital design and implementation of multi-channel filter banks, fft based demodulators, direct digital synthesis, MPSOC applications, high bandwidth interfaces (GigE, PCIe, and JSED), integration, and verification targeting the newest and highest density products from Xilinx and Altera. Senior Design Engineer is responsible for the architecture and implementation of EWS FPGA and ASIC designs. These algorithms require the ability to take advantage of Xilinx/Altera specific architecture features in order to meet requirements in large footprint FPGA components. The selected candidate will be required to develop simulation and lab functional testing in various software environments requiring familiarity with scripting and COTS test software. This candidate is expected to act as a mentor for less experienced FPGA engineers and provide their expertise to Program leadership to support productive program execution. Job duties include but not limited to:
  • Candidate will join an engineering organization focused on RF Electronic Warfare Systems
  • Candidate will be responsible for applying advanced technical principles and concepts to architect and develop FPGA designs based on high level system requirements.
  • Candidate will have the ability to present, explain, and refine architectural approaches in consultation with other product stakeholders
  • Candidate will have the ability to determine and follow the course of action necessary to implement finished products based on the architecture developed.
  • Tasks will include development of Firmware Requirements, Specifications for FPGA designs, VHDL/Verilog-based RTL and functional design, timing analysis, simulation, and integration of FPGA designs into hardware. Other responsibilities include presentation of architecture trade offs, trade studies, design documentation, and mentoring of junior engineers.
Required Skills:
  • 6+ years of professional engineering experience
  • Experience in developing optimal FPGA architectures based on high level requirements
  • Experience with hardware/firmware/software integration and test using FPGAs and embedded processors
  • Proficiency with VHDL/Verilog for configuring FPGAs
  • Experience with FPGA and CPLD development tools from Xilinx, Altera, and MicroSemi
  • Proficiency with Questa/Modelsim for functional verification
  • Experience working in a system integration environment, verifying requirements and identifying and correcting defects
  • U.S. Citizenship status is required as this position requires an Active Secret DoD security clearance on day 1 of employment
  • An active in scope DoD Secret Clearance is required
Desired Skills:
  • Familiarity with digital receiver implementation
  • Familiarity with implementation of digital signal processing algorithms
  • Linux scripting experience
  • Familiarity with Lab testing tools such as LabView and Matlab
  • Experience incorporating third party IP into FPGA designs, including PCIe and high speed Ethernet
  • Familiarity with code coverage tools for evaluating test coverage
Required Education (including Major):
  • Bachelors of Science degree in Electrical Engineering, Computer Engineering or equivalent
Desired Education:
  • Advanced degrees in related fields or technology

Raytheon is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, age, color, religion, creed, sex, sexual orientation, gender identity, national origin, disability, or protected Veteran status.

Company Name:
Security Clearance:
Dallas, Texas
United States
Not Specified
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