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Electrical Engineer I/II Verification

The Verification Electrical Engineers must be able to develop technical solutions to complex problems that require the regular use of ingenuity and creativity. As the CDL Department deploys our Universal Verification Methodology (UVM) based verification capability, we need Verification Electrical Engineers to participate in the functional verification of ASICs/FPGAs as-needed. The Verification Electrical Engineer will create the verification plan with the Program and Register-Transfer Level (RTL) designers input and review in addition to developing the architecture and design of the environment. This requires creating the necessary run and/or post-processing scripts as well as the overall methodology for the given project in terms of the logistics related to using the verification environment. You will also participate in a team of engineers to implement the test benches. The Verification Electrical Engineer will also be involved in the implementation of the verification environment which may include: Creation of Constrained Random Agents; Creation of Monitors, coverage collectors, and Scoreboards; Incorporation of available models that may exist as C/C++, Verilog or VHDL, etc., and/or creation of those models; Creation of functional coverage through use of assertions; Use of functional and code coverage as a quantitative measure to analyze and help determine what is considered 100% coverage for the given design as determined by the verification plan; Writing directed and constrained random tests in parallel with RTL designers to help achieve coverage goals; and use of trouble reports and bug tracking.

Please Note: This position can be an Electrical Engineer I or Electrical Engineer II based on the candidate's qualifications as they relate to the skills, experience and responsibility requirements for the position.

Position is located in Huntsville, AL

Required Skills:

U.S. Citizenship is required
Experience with a scripting languages and utilities such as Make, Perl, Python, or Tcl
Experience with a HDL languages such as Verilog and VHDL
Experience with the HVL language System Verilog
Experience with Questa/Modelsim, VCS and/or NCsim
Experience working in a team environment
Self-directed – Able to complete tasks with minimal oversight
Strong written and verbal communication
A minimum of 1 year of applicable experience

Desired Skills:

Experience reading code and performing modifications in either C or C++ and using DPI/PLI/FLI

Verification in a DoD-Aerospace environment
Knowledge of embedded systems design using PPC40X, Microblaze, Nios or ARM processors
Knowledge of Digital Signal Processing techniques and implementations
Knowledge of industry standard protocols such as AXI, AMBA, PCIe, Ethernet, SPI, I2C, etc.
FPGA design experience using a Linux based development environment

Required Education (including Major):

Bachelor of Science degree in Computer or Electrical Engineering with a minimum of 1 year of relevant experience

Master of Science degree in Computer or Electrical Engineering from an ABET accredited curriculum with a 3.0 GPA or higher and advanced course work related to verification.

This position requires the ability to obtain and hold a DoD secret security clearance.

This position requires the successful issuance, transfer or maintenance of any clearances and/or accesses necessary for the position. Non-US citizens may not be eligible to obtain a security clearance. The Defense Industrial Security Clearance Office (DISCO), an agency of the Department of Defense, handles and adjudicates the security clearance process. Security clearance factors include, but are not limited to, allegiance to the US, foreign influence, foreign preference, criminal conduct, security violations and drug involvement. Additional detail regarding security clearance factors can be obtained by accessing the DISCO website at:

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Huntsville area information:
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Raytheon is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, sex, sexual orientation, gender identity, national origin, disability, or protected Veteran status.


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